View AD8188Z-EVALZ_2673109.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

350 mhz single-supply (5 v) triple 2:1 multiplexers ad8188/ad8189 features fully buffered inputs and outputs fast channel-to-channel switching: 4 ns single-supply operation (5 v) high speed 350 mhz bandwidth (?3 db) @ 200 mv p-p 300 mhz bandwidth (?3 db) @ 2 v p-p slew rate: 1000 v/s fast settling time: 7 ns to 0.1% low current: 19 ma/20 ma excellent video specifications: load resistor (r l ) = 150 differential gain error: 0.05% differential phase error: 0.05 low glitch all hostile crosstalk ?84 db @ 5 mhz ?52 db @ 100 mhz high off isolation: ?95 db @ 5 mhz low cost fast, high impedance disable feature for connecting multiple outputs logic-shifted outputs applications switching rgb in lcd and plasma displays rgb video switchers and routers functional block diagram 24 23 22 21 20 19 18 17 16 15 14 13 v cc v cc dv cc v ee out2 v cc out1 v ee out0 v cc sel a/b oe 1 2 3 4 5 6 7 8 9 10 11 12 in0a in0b v ee in1b v ee in2b v ee v cc in2a v ref in1a d gnd 0 1 2 ad8188/ad8189 enable select logic 06239-001 figure 1. general description the ad8188 (g = 1) and ad8189 (g = 2) are high speed, single-supply, triple 2-to-1 multiplexers. they offer ?3 db small signal bandwidth of 350 mhz and ?3 db large signal bandwidth of 300 mhz, along with a slew rate in excess of 1000 v/s. with ?84 db of all hostile crosstalk and ?95 db off isolation, the parts are well suited for many high speed applications. the differential gain and differential phase error of 0.05% and 0.05 respectively, along with 0.1 db flatness to 70 mhz, make the ad8188 and ad8189 ideal for professional and component video multiplexing. the parts offer 4 ns switching time, making them an excellent choice for switching video signals, while consuming less than 20 ma on a single 5 v supply (100 mw). both devices have a high speed disable feature that sets the outputs into a high impedance state. this allows the building of larger input arrays while minimizing off-channel output loading. the devices are offered in a 24-lead tssop. 4.0 ?1.0 6.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) input output 06239-002 figure 2. ad8189 video amplitude pulse response, v out = 1.4 v p-p, r l = 150 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved.
ad8188/ad8189 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal resistance ...................................................................... 5 maximum power dissipation ..................................................... 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 14 high impedance disable ........................................................... 14 off isolation ................................................................................ 14 full power bandwidth vs. ?3 db large signal bandwidth ... 14 single-supply considerations................................................... 14 ac-coupled inputs.................................................................... 16 tolerance to capacitive load.................................................... 16 secondary supplies and supply bypassing ............................. 16 split-supply operation .............................................................. 16 applications..................................................................................... 17 single-supply operation ........................................................... 17 ac-coupling............................................................................... 17 dc restore .................................................................................. 19 high speed design considerations ......................................... 20 evaluation board ............................................................................ 21 schematics................................................................................... 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 10/06revision 0: initial version
ad8188/ad8189 rev. 0 | page 3 of 24 specifications t a = 25c. for the ad8188, v s = 5 v, r l = 1 k to 2.5 v. for the ad8189, v s = 5 v, v ref = 2.5 v, r l = 150 to 2.5 v; unless otherwise noted. table 1. ad8188/ad8189 parameter conditions min typ max unit dynamic performance ?3 db bandwidth (small signal) v out = 200 mv p-p 350 mhz ?3 db bandwidth (large signal) v out = 2 v p-p 300 mhz 0.1 db flatness v out = 200 mv p-p 70 mhz slew rate (10% to 90% rise time) v out = 2 v p-p, r l = 150 1000 v/s settling time to 0.1% v in = 1 v step, r l = 150 6/7.5 ns noise/distortion performance differential gain 3.58 mhz, r l = 150 0.05 % differential phase 3.58 mhz, r l = 150 0.05 degrees all hostile crosstalk 5 mhz ?84/?78 db 100 mhz ?52/?48 db channel-to-channel crosstalk, rti 5 mhz ?90/?85 db off isolation 5 mhz ?84/?95 db input voltage noise f = 100 khz to 100 mhz 7/9 nv/hz dc performance voltage gain error no load 0.1 0.3/ 0.6 % voltage gain error matching channel a to channel b 0.04 0.2/ 0.2 % v ref gain error 1 k load 0.04 0.6 % input offset voltage 0.2/0.5 6.5/7.0 mv t min to t max 8.0 mv input offset voltage matching channel a to channel b 0.2 5.0/5.5 mv input offset drift 10/5 v/c input bias current 1.5 4/4 a v ref bias current (ad8189 only) 1.0 a input characteristics input resistance @ 100 khz 1.8/1.3 m input capacitance 0.9/1.0 pf input voltage range (about midsupply) in0a, in0b, in1a, in1b, in2a, in2b 1.2 v v ref +0.9/?1.2 v output characteristics output voltage swing r l = 1 k 3.1/2.8 3.2/3.0 v p-p r l = 150 2.8/2.5 3.0/2.7 v p-p short-circuit current 85 ma output resistance enabled @ 100 khz 0.2/0.35 disabled @ 100 khz 1000/600 k output capacitance disabled 1.5/2.0 pf power supply operating range 3.5 5.5 v power supply rejection ratio +psrr, v cc = 4.5 v to 5.5 v, v ee = 0 v ?72/?61 db ?psrr, v ee = ?0.5 v to +0.5 v, v cc = 5.0 v ?76/?72 db quiescent current all channels on 18.5/19.5 21.5/22.5 ma all channels off 3.5/4.5 4.5/5.5 ma t min to t max , all channels on 15 23 ma switching characteristics channel-to-channel switching time 50% logic to 50% output settling, inxa = +1 v, inxb = ?1 v 3.6/4 ns enable-to-channel on time 50% logic to 50% output settling, input = 1 v 4/3.8 ns
ad8188/ad8189 rev. 0 | page 4 of 24 ad8188/ad8189 parameter conditions min typ max unit disable-to-channel off time 50% logic to 50% output settling, input = 1 v 17/5 ns channel switching transient (glitch) all channels grounded 21/45 mv output enable transient (glitch) all channels grounded 64/118 mv digital inputs logic 1 voltage sel a/ b , oe 1.6 v logic 0 voltage sel a/ b , oe 0.6 v logic 1 input current sel a/ b , oe = 2.0 v 45 na logic 0 input current sel a/ b , oe = 0.5 v 2 a
ad8188/ad8189 rev. 0 | page 5 of 24 absolute maximum ratings table 2. parameter 1 rating supply voltage 5.5 v dv cc to d gnd 5.5 v dv cc to v ee 8.0 v v cc to d gnd 8.0 v in0a, in0b, in1a, in1b, in2a, in2b, v ref v ee v in v cc sel a/ b , oe d gnd v in v cc output short-circuit operation indefinite operating temperature range C40c to +85c storage temperature range C65c to +150c lead temperature range (soldering, 10 sec) 300c 1 specification is for device in free air (t a = 25c). stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja 2 jc unit 24-lead tssop 1 85 20 c/w 1 maximum internal power dissipation (pd) should be derated for ambient temperature (t a ) such that pd < (150c t a )/ ja . 2 ja is on a 4-layer board (2s 2p). maximum power dissipation the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. te mporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. while the ad8188/ad8189 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 3 . 2.5 2.0 1.5 1.0 0.5 0 ?50?40?30?20?100 102030405060708090 maximum power dissipation (w) ambient temperature (c) 06239-003 figure 3. maximum power dissipation vs. temperature esd caution
ad8188/ad8189 rev. 0 | page 6 of 24 pin configuration and fu nction descriptions 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 ad8188/ ad8189 top view (not to scale) v cc v cc dv cc v ee out2 v cc out1 v ee out0 v cc oe in0a in0b v ee in1b v ee in2b v ee v cc in2a v ref in1a d gnd sel a/b 06239-004 figure 4. ad8188/ad8189 pin configuration table 4. pin function descriptions pin no. mnemonic description 1 in0a input, high-z in . routed to out0 when a is selected. 2 d gnd ground reference for digital control circuitry. 3 in1a input, high-z in . routed to out1 when a is selected. 4 v ref ad8188: bypass point for internal reference. does not affect dc level of output. ad8189: input to reference buffers for all channels. can be used to offset the outputs. 5 in2a input, high-z in . routed to out2 when a is selected. 6, 13, 17, 21, 24 v cc positive analog supply. nominally 5 v higher than v ee . 7, 9, 11, 15, 19 v ee negative analog supply. 8 in2b input, high-z in . routed to out2 when b is selected. 10 in1b input, high-z in . routed to out1 when b is selected. 12 in0b input, high-z in . routed to out0 when b is selected. 14 dv cc positive supply for digital control circuitry. referenced to d gnd. 16 out2 output. can connect to in2a, in2b, or disable. 18 out1 output. can connect to in1a, in1b, or disable. 20 out0 output. can connect to in0a, in0b, or disable. 22 sel a/ b logic high selects the three a inputs. logic low selects the three b inputs. 23 oe output enable. logic high enables the three outputs. table 5. truth table sel a/ b oe out 0 0 high-z 1 0 high-z 1 1 inxa 0 1 inxb
ad8188/ad8189 rev. 0 | page 7 of 24 typical performance characteristics 3 ?6 ?5 ?4 ?3 ?2 ?1 0 1 2 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.3 0.1 1 10 100 1k 10k gain (db) flatness (db) frequency (mhz) dut 976? 50? 52.3 ? gain flatness 06239-005 figure 5. ad8188 frequency response, v out = 200 mv p-p, r l = 1 k 1 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0.1 1 10 100 1k gain (db) frequency (mhz) dut 976 ? 150 ? 50? 52.3 ? 06239-006 figure 6. ad8188 frequency response, v out = 2 v p-p, r l = 1 k 1 ?6 ?5 ?4 ?3 ?2 ?1 0 0.1 1 10 100 1k gain (db) frequency (mhz) dut 976 ? 150 ? 50? 52.3 ? +85c +25c ?40c 06239-007 figure 7. ad8188 large signal bandwidth vs. temperature, v out = 2 v p-p, r l = 1 k 1 ?6 ?5 ?4 ?3 ?2 ?1 0 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 0.1 1 10 100 1k 10k normalized gain (db) normalized flatness (db) frequency (mhz) gain flatness 06239-008 figure 8. ad8189 frequency response, v out = 200 mv p-p, r l = 150 1 ?6 ?5 ?4 ?3 ?2 ?1 0 0.1 1 10 100 1k normalized gain (db) frequency (mhz) 06239-009 figure 9. ad8189 frequency response, v out = 2 v p-p, r l = 150 1 ?6 ?5 ?4 ?3 ?2 ?1 0 0.1 1 10 100 1k normalized gain (db) frequency (mhz) ?40c +25c +85c 06239-010 figure 10. ad8189 large signal bandwidth vs. temperature, v out = 2 v p-p, r l = 150
ad8188/ad8189 rev. 0 | page 8 of 24 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 100 1k crosstalk (db) frequency (mhz) 06239-011 figure 11. ad8188 all hostile crosstalk vs. frequency (drive all inxa, listen to output with inxb selected) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 100 1k crosstalk (db) frequency (mhz) 06239-012 figure 12. ad8188 adjacent ch annel crosstalk vs. frequency (drive one inxa, listen to an adjacent output with inxb selected) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 11 01 0 0 off isolation (db) frequency (mhz) 1 k 06239-013 figure 13. ad8188 off isolation vs. frequency (drive inputs with oe tied low) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 0.1 1 10 100 1k crosstalk (db) frequency (mhz) 06239-014 figure 14. ad8189 all hostile crosstalk vs. frequency (drive all inxa, listen to output with inxb selected) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 0.1 1 10 100 1k crosstalk (db) frequency (mhz) 06239-015 figure 15. ad8189 adjacent ch annel crosstalk vs. frequency (drive one inxa, listen to an adjacent output with inxb selected) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?120 ?110 11 01 0 0 off isolation (db) frequency (mhz) 1 k 06239-016 figure 16. ad8189 off isolation vs. frequency (drive inputs with oe tied low)
ad8188/ad8189 rev. 0 | page 9 of 24 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 11 0 distortion (dbc) frequency (mhz) 1 0 0 third second 06239-017 figure 17. ad8188 thd vs. frequency, v out = 2 v p-p, r l = 150 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 0.01 1 0.1 100 10 psrr (dbc) frequency (mhz) ?psrr +psrr 06239-018 figure 18. ad8188 psrr vs. frequency, r l = 150 20 18 16 14 12 10 8 6 4 2 0 0.01 1 0.1 10k 10 100 1k noise (nv/ hz) frequency (mhz) 06239-019 figure 19. ad8188 input voltage noise vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 11 0 distortion (dbc) frequency (mhz) 1 0 0 third second 06239-020 figure 20. ad8189 thd vs. frequency, v out = 2 v p-p, r l = 150 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 0.01 1 0.1 100 10 psrr (dbc) frequency (mhz) ?psrr +psrr 06239-021 figure 21. ad8189 psrr vs. frequency, r l = 150 20 18 16 14 12 10 8 6 4 2 0 0.01 1 0.1 10k 10 100 1k noise (nv/ hz) frequency (mhz) 06239-022 figure 22. ad8189 input voltage noise vs. frequency
ad8188/ad8189 rev. 0 | page 10 of 24 10k 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance (k ? ) frequency (mhz) 06239-023 figure 23. ad8188 input impedance vs. frequency 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance ( ? ) frequency (mhz) 06239-024 figure 24. ad8188 enabled ou tput impedance vs. frequency 10k 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance (k ? ) frequency (mhz) 06239-025 figure 25. ad8188 disabled ou tput impedance vs. frequency 10k 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance (k ? ) frequency (mhz) 06239-026 figure 26. ad8189 input impedance vs. frequency 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance ( ? ) frequency (mhz) 06239-027 figure 27. ad8189 enabled ou tput impedance vs. frequency 10k 1k 100 10 1 0.1 0.1 1 1k 10 100 impedance (k ? ) frequency (mhz) 06239-028 figure 28. ad8189 disabled ou tput impedance vs. frequency
ad8188/ad8189 rev. 0 | page 11 of 24 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 3.3 2.8 2.3 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-029 figure 29. ad8188 small signal pulse response, v out = 200 mv p-p, r l = 1 k 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-030 figure 30. ad8188 video amplitude pulse response, v out = 700 mv p-p, r l = 1 k 4.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 7.0 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-031 figure 31. ad8188 large signal pulse response, v out = 2 v p-p, r l = 1 k 2.8 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3.2 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-032 figure 32. ad8189 small signal pulse response, v out = 200 mv p-p, r l = 150 k 4.0 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-033 figure 33. ad8189 video amplitude pulse response, v out = 1.4 v p-p, r l = 150 k 4.0 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 input voltage (v) output voltage (v) time (ns) output input 06239-034 figure 34. ad8189 large signal pulse response, v out = 2 v p-p, r l = 150 k
ad8188/ad8189 rev. 0 | page 12 of 24 output (1mv/div) time (2ns/div) t 0 t settled 06239-035 figure 35. ad8188 settling time (0.1%), v out = 2 v step, r l = 1 k 2.3 ?2.8 ?2.3 ?1.8 ?1.3 ?0.8 ?0.3 0.3 0.8 1.3 1.8 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 select a/b pulse amplitude (v) output amplitude (v) time (ns) output sel a/b 06239-036 figure 36. ad8188 channel-to-channel switching time, v out = 2 v p-p, inxa = 3.5 v, inxb = 1.5 v 2.0 ?1.0 ?0.5 0 1.5 1.0 0.5 3.0 2.4 2.5 2.6 2.7 2.8 2.9 05 0 454035302520 1510 5 select a/b pulse amplitude (v) output amplitude (v) time (ns) output sel a/b 06239-037 figure 37. ad8188 channel switching transient (glitch), inxa = inxb = 0 v output (1mv/div) time (2ns/div) t 0 t settled 06239-038 figure 38. ad8189 settling time (0.1%), v out = 2 v step, r l = 150 2.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0 5 10 15 20 25 select a/b pulse amplitude (v) output amplitude (v) time (ns) output 06239-039 sel a/b figure 39. ad8189 channel-to-channel switching time, v out = 2 v p-p, inxa = 3.0 v, inxb = 2.0 v 2.0 ?1.0 ?0.5 0 1.5 1.0 0.5 3.0 2.4 2.5 2.6 2.7 2.8 2.9 05 0 454035302520 1510 5 select a/b pulse amplitude (v) output amplitude (v) time (ns) output sel a/b 06239-040 figure 40. ad8189 channel switching transient (glitch), inxa = inxb = v ref = 0 v
ad8188/ad8189 rev. 0 | page 13 of 24 180 160140120 100 806040 20 oe pulse amplitude (v) output amplitude (v) time (ns) 2.0 1.5 1.0 0.5 0 ?0.5 ?1.5 ?1.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 02 0 0 output oe 06239-041 figure 41. ad8188 enable on/off time, v out = 0 v to 1 v 1.5 1.0 0 0.5 3.0 2.9 2.8 2.7 2.6 2.5 2.4 05 0 2.0 1.0 1.5 0.5 0 ?0.5 ?1.0 ?2.0 ?1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 0 200 180 160140120 100 806040 20 oe pulse amplitude (v) output amplitude (v) time (ns) output oe 06239-043 45403530 25 201510 5 oe pulse amplitude (v) output amplitude (v) time (ns) output oe 06239-042 figure 42. ad8188 channel enable/disable transient (glitch) figure 43. ad8189 enable on/off time, v out = 0 v to 1 v 2.0 ?1.0 ?0.5 0 0.5 1.0 1.5 3.0 2.9 2.8 2.7 2.6 2.5 2.4 05 0 45403530 25 201510 5 oe pulse amplitude (v) output amplitude (v) time (ns) output oe 06239-044 figure 44. ad8189 channel enable/disable transient (glitch)
ad8188/ad8189 rev. 0 | page 14 of 24 theory of operation the ad8188 (g = 1) and ad8189 (g = 2) are single-supply, triple 2:1 multiplexers with ttl-compatible global input switching and output-enable control. optimized for selecting between two rgb (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution. the multiplexers also have respectable video specifications and are superior for switching ntsc or pal composite signals. the multiplexers are organized as three independent channels, each with two input transconductance stages and one output transimpedance stage. the appropriate input transconductance stages are selected via one logic pin (sel a/ b ) such that all three outputs simultaneously switch input connections. the unused input stages are disabled with a proprietary clamp circuit to provide excellent crosstalk isolation between on and off inputs while protecting the disabled devices from damaging reverse base-emitter voltage stress. no additional input buffering is necessary, resulting in low input capacitance and high input impedance without additional signal degradation. the transconductance stage is a high slew rate, class ab circuit that sources signal current into a high impedance node. each output stage contains a compensation network and is buffered to the output by a complementary emitter-follower stage. voltage feedback sets the gain with the ad8188 configured as a unity gain follower, and the ad8189 configured as a gain-of-two amplifier with a feedback network. this architecture provides drive for a reverse-terminated video load (150 ) with low differential gain and phase errors, while consuming relatively little power. careful chip layout and biasing result in excellent crosstalk isolation between channels. high impedance disable the output-enable logic pin (oe) of the ad8188 and ad8189 controls whether the three outputs are enabled or disabled to a high impedance state. the high impedance disable allows larger matrices to be built by busing the outputs together. in the case of the ad8189 (g = 2), the reference buffers also disable to a state of high output impedance. this feature prevents the feedback network of a disabled channel from loading the output, which is valuable when busing together the outputs of several muxes. off isolation the off isolation performance of the signal path is dependent upon the value of the load resistor, r l . for calculating off isolation, the signal path can be modeled as a simple high-pass network with an effective capacitance of 3 ff. off isolation improves as the load resistance is decreased. in the case of the ad8188, off isolation is specified with a 1 k load. however, a practical application would likely gang the outputs of multiple muxes. in this case, the proper load resistance for the off isolation calculation is the output impedance of an enabled ad8188, typically less than a 1/10 . full power bandwidth vs. ?3 db large signal bandwidth note that full power bandwidth for an undistorted sinusoidal signal is often calculated using the peak slew rate from the equation amplitude sinusoid rateslewpeak bandwidth powerfull = 2 the peak slew rate is not the same as the average slew rate. the average slew rate is typically specified as the ratio t v out measured between the 20% and 80% output levels of a sufficiently large output pulse. for a natural response, the peak slew rate can be 2.7 times larger than the average slew rate. therefore, calculating a full power bandwidth with a specified average slew rate gives a pessimistic result. see the specifications section for the large-signal bandwidth and average slew rate for both the ad8188 and ad8189 (large signal bandwidth is defined as the ?3 db point measured on a 2 v p-p output sine wave). figure 17 and figure 20 contain plots for the second- and third- order harmonic distortion. specifying these three aspects of the signal paths large signal dynami cs allows the user to predict system behavior for either pulse or sinusoid waveforms. single-supply considerations the ad8188 and ad8189 offer superior large signal dynamics. the trade-off is that the input and output compliance is limited to ~1.3 v from either rail when driving a 150 load. the following sections address some challenges of designing video systems within a single 5 v supply. the ad8188 the ad8188 is internally wired as a unity-gain follower. its inputs and outputs can both swing to within ~1.3 v of either rail. this affords the user 2.4 v of dynamic range at input and output that should be enough for most video signals, whether the inputs are ac- or dc-coupled. in both cases, the choice of output termination voltage determines the quiescent load current. for improved supply rejection, the v ref pin should be tied to an ac ground (the more quiet the supply, the better). internally, the v ref pin connects to one terminal of an on-chip capacitor. the capacitors other terminal connects to an internal node. the consequence of building this bypass capacitor on-chip is twofold. first, the v ref pin on the ad8188 draws no input bias current. (contrast this to the case of the ad8189, where the v ref pin typically draws 2 a of input bias current.) second, on the ad8188, the v ref pin can be tied to any voltage within the supply range.
ad8188/ad8189 rev. 0 | page 15 of 24 in0a in0b in1b in1a in2a in2b out0 out1 out2 ad8188 mux system ?c_bypass? v ref internal cap bias reference direct connection to any ?quiet? ac ground (for example, gnd, v cc , and v ee ). 06239-045 figure 45. v ref pin connection for ad8188 (differs from ad8189) the ad8189 the ad8189 uses on-chip feedback resistors to realize the gain- of-two function. to provide low crosstalk and a high output impedance when disabled, each set of 500 feedback resistors is terminated by a dedicated reference buffer. a reference buffer is a high speed op amp configured as a unity-gain follower. the three reference buffers, one for each channel, share a single, high impedance input, the v ref pin (see figure 46 ). v ref input bias current is typically less than 2 a. out1 out0 out2 a0 b0 v ref 5 v 5v 5v gbuf 0 5v gbuf 1 5v gbuf 2 500 ? 500 ? 500? 500? 500? 500? vf-2 vf-1 1 vfo 06239-046 figure 46. conceptual diagram of a single multiplexer channel, g = 2 this configuration has a few implications for single-supply operation: x on the ad8189, v ref cannot be tied to the most negative analog supply, v ee . the limits on reference voltage are (see figure 47 ): v ee + 1.3 v < v ref v cc ? 1.6 v 1.3 v < v ref , 3.4 v on 0 v/5 v supplies a0 v ref 5v 5v out0 5 v v o_max = 3.7v v o_min = 1.3v v o_min = 1.3v v o_max = 3.4v 5v 1.3v 1.3v 1.3v 1.6v gnd gnd v out v ref 0 6239-047 figure 47. output compliance of main amplifier channel and ground buffer x the signal at the v ref pin appears at each output. therefore, v ref should be tied to a well bypassed, low impedance source. using superposition, it is shown that v out = 2 v in ? v ref x to maximize the output dynamic range, the reference voltage should be chosen with care. for example, consider amplifying a 700 mv video signal with a sync pulse 300 mv below black level. if the user decides to set v ref at black level to preferentially run video signals on the faster npn transistor path, the ad8189 allows a reference voltage as low as 1.3 v + 300 mv = 1.6 v. if the ad8189 is used, the sync pulse is amplified to 600 mv. therefore, the lower limit on v ref becomes 1.3 v + 600 mv = 1.9 v. for routing rgb video, an advantageous configuration is to employ +3 v and ?2 v supplies, in which case v ref can be tied to ground. if system considerations prevent running the multiplexer on split supplies, a false ground reference should be employed. a low impedance reference can be synthesized with a second operational amplifier. alternately, a well bypassed resistor divider can be used. refer to the applications section for further explanation and more examples. v ref 0.022f 5 v gnd op21 100k ? 10k? 100 ? from 1992 adi amplifier applications guide 1f 1f 06239-048 figure 48. synthesis of a false ground reference
ad8188/ad8189 rev. 0 | page 16 of 24 v ref 5 v 10k ? 10k ? 1f cap must be large enough to absorb transient currents with minimum bounce. 06239-049 figure 49. alternate method for synthesis of a false ground reference ac-coupled inputs using ac-coupled inputs presents an interesting challenge for video systems operating from a single 5 v supply. in ntsc and pal video systems, 700 mv is the approximate difference between the maximum signal voltage and black level. it is assumed that sync has been stripped. however, given the two pathological cases shown in figure 50 , a dynamic range of twice the maximum signal swing is required if the inputs are to be ac-coupled. a possible solution is to use a dc restore circuit before the mux. +700mv ?700mv +5v gnd v avg v avg v signal v ref v ref white line with black pixel black line with white pixel v input = v ref + v signal v ref ~ v avg v ref is a dc voltage set by the resistors 06239-050 figure 50. pathological case for input dynamic range tolerance to capacitive load op amps are sensitive to reactive loads. a capacitive load at the output appears in parallel with an effective resistance (r eff ) of r eff = ( r l || r o ) where r l is the discrete resistive load, and r o is the open loop output impedance, approximately 15 for these muxes. the load pole (f load ) at leff load cr f s 2 1 can seriously degrade phase margin and, therefore, stability. the old workaround is to place a small series resistor directly at the output to isolate the load pole. while effective, this ruse also affects the dc and termination characteristics of a 75 system. the ad8188 and ad8189 are built with a variable compensation scheme that senses the output reactance and trades bandwidth for phase margin, ensuring faster settling and lower overshoot at higher capacitive loads. secondary supplies and supply bypassing the high current output transistors are given their own supply pins (pin 15, pin 17, pin 19, and pin 21) to reduce supply noise on-chip and to improve output isolation. because these secondary, high current supply pins are not connected on-chip to the primary analog supplies, v cc /v ee (pin 6, pin 7, pin 9, pin 11, pin 13, and pin 24), some care should be taken to ensure that the supply bypass capacitors are connected to the correct pins. at a minimum, the primary supplies should be bypassed. pin 6 and pin 7 can be a convenient place to accomplish this. stacked power and ground planes are a convenient way to bypass the high current supply pins (see figure 51 ). mux1 mux2 mux3 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 0.1 f 1f v cc v cc dv cc v ee out2 v cc out1 v ee out0 v cc oe in0a in0b v ee in1b v ee in2b v ee v cc in2a v ref in1a d gnd sel a/b 06239-051 figure 51. detail of primary and secondary supplies split-supply operation operating from split supplies (for example, [+3 v/?2 v] or 2.5 v) simplifies the selection of the v ref voltage and load resistor termination voltage. in this case, it is convenient to tie v ref to ground. the logic inputs are internally level-shifted to allow the digital supplies and logic inputs to operate from 0 v and 5 v when powering the analog circuits from split supplies. the maximum voltage difference between dv cc and v ee must not exceed 8 v (see figure 52 ). 8v max (+5v) (0v) (+2.5v) (?2.5v) dv cc d gnd v cc v ee digital supplies analog supplies 06239-052 figure 52. split-supply operation
ad8188/ad8189 rev. 0 | page 17 of 24 applications single-supply operation the ad8188/ad8189 are targeted mainly for use in single- supply 5 v systems. for operating on these supplies, both v ee and d gnd should be tied to ground, and the control logic pins should be referenced to ground. normally, the dv cc supply needs to be set to the same positive supply as the driving logic. for dc-coupled, single-supply operation, it is necessary to set an appropriate input dc level that is within the specified range of the amplifier. for the unity-gain ad8188, the output dc level is the same as the input, while for the gain-of-two ad8189, the v ref input can be biased to obtain an appropriate output dc level. figure 53 shows a circuit that provides a gain-of-two and is dc-coupled. the video input signals must have a dc bias from their source of approximately 1.5 v. this same voltage is applied to v ref of the ad8189. the result is that when the video signal is at 1.5 v, the output is also at the same voltage. this is close to the lower dynamic range of both the input and the output. when the input goes most positive, which is 700 mv above the black level for a standard video signal, it reaches a value of 2.2 v, and there is enough headroom for the signal. on the output side, the magnitude of the signal changes by 1.4 v, making the maximum output voltage 2.2 v + 1.4 v = 3.6 v. this is just within the dynamic range of the output of the part. ac-coupling ad8188 when a video signal is ac-coupled, the amount of dynamic range required to handle the signal can potentially be double the amount required for dc-coupled operation. for the unity- gain ad8188, there is still enough dynamic range to handle an ac-coupled, standard video signal with 700 mv p-p amplitude. if the input is biased at 2.5 v dc, the input signal can potentially go 700 mv both above and below this point. the resulting 1.8 v and 2.2 v are within the input signal range for single 5 v operation. because the part is unity-gain, the outputs follow the inputs, and there is adequate range at the output as well. when the ad8188 is operated from a single supply of 5 v and ground, ac-coupling is often useful. this is particularly true when the input signals are a typical rgb source from a pc. these signals go all the way to ground at the most negative, outside of the ad8188 input range, when its negative supply is ground. the closest that the input can go to ground is typically 1.3 v. there are several basic methods for ac-coupling the inputs. they all consist of a series capacitor followed by a circuit for setting the dc operating point of the input and then the ad8188 input. if a termination is provided, it should be located before the series coupling capacitor. the different circuits vary in the means used to establish the dc operating point after the coupling capacitor. a straightforward way to do this is to use a voltage divider for each input. however, because there are six inputs altogether, 12 resistors are required to set all of the dc operating points. this means many components in a small space, but the circuit has the advantage of having the lowest crosstalk among any of the inputs. this circuit is shown in figure 54 . a circuit that uses the minimum number of resistors can be designed. first, create a node, v mid , which serves as the bias voltage for all of the inputs. then, a single resistor is used to connect from each input (inside the ac-coupling capacitor) and v mid (see figure 55 ). v ee d gnd red grn blu reda grna blua in2b in1b in0b in0a in1a in2a v ref 5v 1.5v 1.5k ? 3.48k ? blub grnb redb dv cc sel a/b oe 2 out0 out1 out2 v cc 2 2 0.7v max black level black level 2.2v 1.5v typical input levels (all 6 outputs) typical output levels (all 3 outputs) 3.0v 1.4v max 1.5v ad8189 3v to 5 v 5 v 06239-055 figure 53. ad8189 dc-coupled (b ypassing and logic not shown)
ad8188/ad8189 rev. 0 | page 18 of 24 v ee d gnd in2b in2a in0a in0b in1a dv cc oe v cc sel a/b ad8188 5 v 5 v v ref in1b to a/d, etc. + ? + ? + ? 10f 0.1f 0.1f out0 out1 out2 rgb s ource a r g b rgb s ource b r g b 4.99k ? 5v 0.1f 4.99k ? 75 ? 0.1f 4.99k ? 75 ? 0.1f 4.99k ? 75 ? 0.1f 4.99k ? 75 ? 0.1f 4.99k ? 75 ? 0.1f 4.99k ? 75 ? hi = enable lo = disable hi = a lo = b 4.99k ? 5v 4.99k ? 5v 4.99k ? 5v 4.99k ? 5v 4.99k ? 5v 0 6239-053 figure 54. ad8188 ac-coupling us ing separate voltage dividers v ee d gnd in2b in2a in0a in0b in1a dv cc oe v cc sel a/b ad8188 5 v 5 v v ref in1b to a/d, etc. + ? + ? + ? 10f 0.1f 0.1f out0 out1 out2 rgb s ource a r g b rgb s ource b r g b 0.1f 75? 0.1f 75? 0.1f 75? 0.1f 75? 0.1f 75? 0.1f 75? hi = enable lo = disable hi = a lo = b 100? 100? 0.1f 10f 5v v mid 4.99k ? v mid 4.99k ? v mid 4.99k ? v mid 4.99k ? v mid 4.99k ? v mid 4.99k ? v mid 06239-054 figure 55. ad8188 ac-coupling using a single v mid reference the circuit in figure 55 can increase the crosstalk between inputs, because each input signal creates a small signal on v mid due to its nonzero impedance. there are several means to minimize this. first, make the impedance of the v mid divider small. small resistor values lower the dc resistance, and good bypassing to ground minimizes the ac impedance. it is also possible to use a voltage regulator or another system supply voltage if it is the correct value. it should be close to the mid- supply voltage of the ad8188. the second technique for minimizing crosstalk is to use large resistor values to connect from the inputs to v mid . the major factor limiting the value of these resistors is offset caused by the input bias current (i b ) that must flow through these resistors to the ad8188 inputs. the typical i b for an ad8188 input is 1.5 a, which causes an offset voltage of 1.5 mv per 1 k of resistance.
ad8188/ad8189 rev. 0 | page 19 of 24 these two techniques can also be combined. typically, crosstalk between the rgb signals from the same source is less objectionable than crosstalk between two different sources. the former can cause a color or luminance shift, but spatially, everything is coherent. however, the crosstalk signals from two uncorrelated sources can create ghost images that are far more objectionable. a technique for minimizing crosstalk between two different sources is to create two separate v mid circuits. then, the inputs from each source can be connected to their own v mid node, minimizing crosstalk between sources. ad8189 when using the gain-of-two ad8189 in a simple ac-coupled application, there is a dynamic range limitation at the output caused by its higher gain. at the output, the gain-of-two produces a signal swing of 1.4 v, but the ac-coupling doubles this required amount to 2.8 v. the ad8189 outputs can only swing from 1.4 v to 3.6 v on a 5 v supply, so there are only 2.2 v of dynamic signal swing available at the output. a standard means for reducing the dynamic range requirements of an ac-coupled video signal is to use a dc restore. this circuit works to limit the dynamic range requirements by clamping the black level of the video signal to a fixed level at the input to the amplifier. this prevents the video content of the signal from varying the black level, as happens in a simple ac-coupled circuit. dc restore after ac-coupling a video signal, it is necessary to use a dc restore to establish where the black level is. usually, this appears at the end of a video signal chain. this dc restore circuit needs to have the required accuracy for the system. it compensates for all the offsets of the preceding stages. therefore, if a dc restore circuit is to be used only for dynamic range limiting, it does not require great dc accuracy. a dc restore circuit using the ad8189 is shown in figure 56 . two separate sources of rgb video are ac-coupled to the 0.1 f input capacitors of the ad8189. the input points of the ad8189 are switched to a 1.5 v reference by the adg786, which works in the following manner: ? the sel a/ b signal selects the a or b input to the ad8189. it also selects the switch positions in the adg786 such that the same selected inputs are connected to v ref when en is low. ? during the horizontal interval, all of the rgb input signals are at a flat black level. a logic signal that is low during hsync is applied to the en of the adg786. this closes the switches and clamps the black level to 1.5 v. at all other times, the switches are off and the node at the inputs to the ad8189 floats. there are two considerations for sizing the input coupling capacitors. one is the time constant during the h-pulse clamping. the other is the droop associated with the capacitor discharge due to the input bias current of the ad8189. for the former, it is better to have a small capacitor, but for the latter, a larger capacitor is better. the on resistance of the adg786 and the coupling capacitor form the time constant of the input clamp. the adg786 on resistance is 5 maximum. with a 0.1 f capacitor, a time constant of 0.5 s is created. thus, a sync pulse of greater than 2.5 s causes less than 1% error. this is not critical because the black level from successive lines is very close and the voltage changes little from line to line. a rough approximation of the horizontal line time for a graphics system is 30 s. this varies depending on the resolution and the vertical rate. the coupling capacitor needs to hold the voltage relatively constant during this time, while the input bias current of the ad8189 discharges it. the change in voltage is i b times the line time divided by the capacitance. with an i b of 2.5 a, a line time of 30 s, and a 0.1 f coupling capacitor, the amount of droop is 0.75 mv. this is roughly 0.1% of the full video amplitude and is not observable in the video display. v ee d gnd red grn blu reda grna blua in2b in1b in0b in0a in1a in2a v ref v ref blub grnb redb dv cc sel a/b oe 2 out0 out1 out2 v cc 2 2 ad8189 3v to 5 v 5 v 0.1f 0.1f 0.1f 0.1f 0.1f 0.1f s1a s1b s2a s2b s3a s3b v dd 5v d1 d2 d3 gnd v ss en a0 a1 a2 + 5v 1.5k ? 3.48k ? 1.5v v ref 10f 0.1f adg786 logic sel a/b hsync 2.4v min 0.8v min 0 6239-056 figure 56. ad8189 ac-coupled with dc restore
ad8188/ad8189 rev. 0 | page 20 of 24 high speed design considerations the ad8188/ad8189 are extremely high speed switching amplifiers for routing the highest resolution graphic signals. extra care is required in the circuit design and layout to ensure that the full resolution of the video is realized. first, the board should have at least one layer of a solid ground plane. long signal paths should be referenced to a ground plane as controlled-impedance traces. all bypass capacitors should be very close to the pins of the part with minimum extra circuit length in the path. it is also helpful to have a large v cc plane on a circuit board layer that is closely spaced to the ground plane. this creates a low inductance interplane capacitance, which is very helpful in supplying the fast transient currents that the part demands during high resolution signal transitions.
ad8188/ad8189 rev. 0 | page 21 of 24 evaluation board an evaluation board has been designed and is offered for running the ad8188/ad8189 on a single supply. the inputs and outputs are ac-coupled and terminated with 75 resistors. for the ad8189, a potentiometer is provided to allow setting v ref at any value between v cc and ground. the logic control signals can be statically set by adding or removing a jumper. if a fast signal is required to drive the logic pins, an sma connector can be used to deliver the signal, and a place for a termination resistor is provided. 06239-057 figure 57. component side board layout 06239-058 figure 58. circuit side board layout
ad8188/ad8189 rev. 0 | page 22 of 24 06239-059 figure 59. component side silkscreen 06239-060 figure 60. circuit side silkscreen
ad8188/ad8189 rev. 0 | page 23 of 24 schematics 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 dut w1 oe sel a/b out2 out1 out0 w2 gnd1 gnd2 gnd3 gnd4 c1 0.1f c4 0.1f c5 0.1f c13 10f c3 0.1f c6 0.1f c8 0.1f c9 0.1f c14 0.01f c24 0.1f in0 a in1 a in2a in2b in1b in0b cw r1 * r10, r12, r14, r19, and r20 not installed on evaluation board for test purposes. r1 is not used for ad8188. r4 75? a gnd a gnd v cc v cc v cc v cc v cc v cc v ref v ref v ref v ref v ref v ref v ref a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd r5 75? a gnd v ref c10 0.1f c15 10f r19* tbd r20* tbd r14* tbd r12* tbd r10* tbd c18 0.1f c7 0.1f c19 0.1f c20 0.1f c17 0.1f c12 0.1f c16 10f r17 4.99k ? r16 4.99k ? r15 4.99k ? r22 4.99k ? r6 75? r18 4.99k ? r7 75? r3 75? r8 75 ? r21 4.99k ? r13 75 ? r11 75 ? r9 75 ? r24 1k? r23 1k? v cc v cc v cc v cc in0a in0b v ee in1b v ee in2b v ee v cc in2a v ref in1a d gnd v cc v cc dv cc v ee out2 v cc out1 v ee out0 v cc oe sel a/b ad8188/ ad8189 06239-061 figure 61. single-su pply evaluation board
ad8188/ad8189 rev. 0 | page 24 of 24 ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06239-0-10/06(0) outline dimensions 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane 0.10 coplanarity compliant to jedec standards mo-153-ad figure 62. 24-lead thin shrink small outline package [tssop] [ru-24] dimensions shown in millimeters ordering guide model temperature range package description package option ad8188aruz 1 C40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad8188aruz-rl 1 C40c to +85c 24-lead thin shrink small outline package [tssop], 13" reel ru-24 ad8188aruz-r7 1 C40c to +85c 24-lead thin shrink small outline package [tssop], 7" reel ru-24 ad8189aruz 1 C40c to +85c 24-lead thin shrink small outline package [tssop] ru-24 ad8189aruz-rl 1 C40c to +85c 24-lead thin shrink small outline package [tssop], 13" reel ru-24 ad8189aruz-r7 1 C40c to +85c 24-lead thin shrink small outline package [tssop], 7" reel ru-24 AD8188Z-EVALZ 1 evaluation board ad8189z-evalz 1 evaluation board 1 z = pb-free part.

▲Up To Search▲

Price & Availability of AD8188Z-EVALZ

	To Download AD8188Z-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .